Wiring congestion in an area of a semiconductor chip can have an adverse impact on timing due to longer than minimum (non-steiner) wire lengths causing larger than necessary wire and circuit delays. Ideally, the placement of an individual circuit should be somewhere between the circuit(s) that drives it and the circuit(s) that it drives. This eliminates the needless consumption of wiring tracks due to cross wiring along the path. Typically, automated placement programs are driven by metrics that result in this condition. However, subsequent steps in the physical design process, such as replication of clock network circuits followed by placement legalization, can lead to situations where circuits are moved outside of their area of connectivity. Steps to replace a particular region to alleviate wiring congestion may negate prior logical or physical design modifications made to improve timing. U.S. Pat. No. 5,859,781 for a “Method and Apparatus For Computing Minimum Wirelength Position (MWP) For Cell in Cell Placement for Integrated Circuit Chip”, describes a method for optimizing the placement of circuits in order to minimize total wire length by employing bounding boxes of connectivity for each net connected to a circuit. Although this is adequate from a pure wirability viewpoint, one drawback is that not all net segments have an equal relationship to timing. Particularly in a design that has gone through some level of logic optimization based on physical design parameters, such as those described in U.S. Pat. No. 6,192,508, “Method For Logic Optimization For Improved Timing and Congestion During Placement In Integrated Circuit Design”, longer length nets have probably already had the circuit driving them bumped up in strength while shorter lengths potentially have smaller/weaker circuits driving them. In this case, decreasing the total net length of a set of nets at the expense of increasing certain pin to pin segments could have an adverse impact on timing. This is illustrated by the two examples shown in FIG. 1. For circuit D1, a placement move to the left will decrease total net length as both nets IN1B and IN2B are reduced by the same length that net OUT1B is increased. However, if circuit D1 is a weak strength circuit, the delay increase due to the longer length of net OUT1B is likely to outweigh the delay decrease due to the shorter lengths of nets IN1B and IN2B, creating a potential timing problem. Even in the case where no net lengths increase, there can still be a timing impact due to an increased pin to pin connection. A placement move to the left for circuit B1 in the figure will decrease the net lengths of nets IN1A and OUT1A and net IN2A's length will remain the same. However, the pin to pin length from A2 to B1 will increase, potentially leading to a larger path delay if the delay of circuit B1 is particularly sensitive to input slew and/or if the magnitude of increase in wire delay from A2 to B1 is greater than the decrease in wire delay from B1 to C1. Such scenarios could require further design iteration to achieve timing closure.